`timescale 1ns / 1ps
`include "const.v"

module IF_ID(
	input clk,
	input reset,
    input en,
    input [31:0] F_instr,
    input [31:0] F_PC,
    input F_isBD,
    output reg [4:0] D_RS,
    output reg [4:0] D_RT,
    output reg [4:0] D_RD,
    output reg [15:0] D_imm16,
    output reg [31:0] D_PC,
    output reg [25:0] D_imm26,
    output reg [31:0] D_instr,
    output reg [4:0] D_shamt,
    output reg D_isBD
    );

	initial begin
		D_RS <= 0;
		D_RT <= 0;
        D_RD <= 0;
		D_imm16 <= 0;
		D_PC <= 0;
		D_imm26 <= 0;
		D_instr <= 0;
        D_shamt <= 0;
        D_isBD <= 0;
	end

    always @(posedge clk) begin
        if(reset) begin
            D_RS <= 0;
		    D_RT <= 0;
		    D_RD <= 0;
		    D_imm16 <= 0;
	//	    D_PC <= 0;
		    D_imm26 <= 0;
		    D_instr <= 0;
            D_shamt <= 0;
            D_isBD <= 0;
        end
        else if(en) begin
            D_RS <= F_instr[`RS];
            D_RT <= F_instr[`RT];
            D_RD <= F_instr[`RD];
            D_imm16 <= F_instr[`OFFSET];
            D_PC <= F_PC;
            D_imm26 <= F_instr[25:0];
            D_instr <= F_instr;
            D_shamt <= F_instr[10:6];
            D_isBD <= F_isBD;
        end
    end

endmodule
